With the end of CMOS scaling in sight, the future road-map for the expansion of computing power remains uncertain. State of the art digital computing systems, which benefited significantly from scaling, actually use area and power inefficiently as they operate transistors at two extreme points. Contrary to digital, analog circuits make use of the entire operating voltage range of the transistor and are highly area and power efficient. Analog computing has long been associated with high variability and linearity issues when implemented onchip. However, sub-threshold gm stages have been shown to be very stable against process, voltage, and temperature variations . We can leverage this technique to come up with high precision analog computing circuits. The current research on analog computing research includes work on high precision multiplier and vector matrix multiplication circuit to realize multilayer convolutional computing infrastructure, logarithmic amplifiers for feature extraction and processing in analog, and variation tolerant critical current and voltage sources and references.
Project is funded through generous supports from NSF and Northeastern.
- Y. Zhang, N. Mirchandani, M. Onabajo, and A. Shrivastava , “RSSI Amplifier Design for a Feature Extraction Technique to Detect Seizures with Analog Computing”, IEEE International Symposium on Circuits and Systems (ISCAS), May-2020, Seville, Spain. (accepted for publication)
- N. Mirchandani and A. Shrivastava , “CMOS based ultra-low Power High-Precision Analog Vector Matrix Multiplication Circuit with +/-0.1% Error for Vision Application”, Mid-West Symposium on Circuits and Systems (MWSCAS), July-2019, Dallas. pdf
- N. Mirchandani and A. Shrivastava , “High Stability Gain Structure and Filter Realization with less than 50 ppm/oC Temperature Variation with Ultra-low Power Consumption using Switched-capacitor and Sub-threshold Biasing”, IEEE International Symposium on Circuits and Systems (ISCAS), May-2018, Florence, Italy. pdf